Development and implementation of the level 0 Pixel Trigger System for the ALICE silicon pixel detector

The silicon pixel detector (SPD) of the ALICE experiment at CERN Large Hadron Collider contains 1200 readout chips. Low latency Fast-OR signals indicate the presence of at least one hit in the 8192 pixel matrix of each chip within 300 ns from the interaction time. The 1200 Fast-OR bits are transmitted every 100 ns on 120 data readout optical links, using the G-Link protocol. The Pixel Trigger System extracts and processes them to deliver an input signal to the Central Trigger Processor within an overall latency of 800 ns from the interaction. Therefore the prompt SPD Fast-OR signals can be used in the first level (Level 0) trigger decision of the experiment. The Pixel Trigger System is very compact, modular and based on FPGA devices. Its architecture allows the user to define and implement various Fast-OR processing algorithms, based on topology and occupancy. The system receiver boards use advanced 12-channel parallel optical fiber receiver modules operating at 1310 nm and 12 deserializer chips closely packed in a small area. This paper describes the development of the Pixel Trigger System with the solutions adopted to satisfy a set of specific requirements. The design constraints, the chosen architecture and a description of the system are detailed first. The implementation of the system and the first integration tests are then presented.