Impact of gate-leakage current noise in sub-100 nm CMOS front-end electronics

In future high energy physics experiments, readout integrated circuits for charged particle tracking systems will be realized by means of CMOS devices belonging to fabrication processes whose minimum feature size is in the 100 nm span. In nanoscale technologies, the reduction of the gate oxide thickness introduces a non-negligible gate current due to direct tunneling phenomena. This leakage current, being caused by discrete charges randomly crossing a potential barrier, results in an increase of the static power consumption for digital circuits and might degrade noise performances in analog applications. As a consequence, in these advanced CMOS processes an accurate characterization of the gate current noise is mandatory in order to establish design criteria for detector front-ends. This work presents the results of static and noise characterization of the gate-leakage current carried out on NMOS devices belonging to a 90 nm commercial process. Data extracted from the measurements have been used to evaluate the impact of this noise source on the resolution limits achievable for low-noise charge sensitive amplifiers within this technology node.