• DocumentCode
    47199
  • Title

    Electrostatic Modeling and Insights Regarding Multigate Lateral Tunneling Transistors

  • Author

    Pan, Andrew ; Songtao Chen ; Chi On Chui

  • Author_Institution
    Dept. of Electr. Eng., Univ. of California, Los Angeles, Los Angeles, CA, USA
  • Volume
    60
  • Issue
    9
  • fYear
    2013
  • fDate
    Sept. 2013
  • Firstpage
    2712
  • Lastpage
    2720
  • Abstract
    We use pseudo-2-D analytical models to study the electrostatics of multigate tunneling field-effect transistors (TFETs), providing a portable set of equations to simultaneously describe silicon-on-insulator, double gate, and cylindrical nanowire devices. We validate the model via extensive comparisons with numerical simulations and demonstrate its accuracy and general applicability; 2-D tunneling effects are analytically estimated and found to be small for well-scaled devices within the semiclassical model. We also study the impact of source and drain doping on TFET performance, including a seminal analytical treatment of nonabrupt junctions and degeneracy effects. We present a new simple model to explain the adverse effects of excessive source doping, and show for the first time how degeneracy in low density-of-states materials directly degrades not only the tunneling efficiency, but also the device electrostatics, causing particular problems for III-V p-TFETs.
  • Keywords
    MOSFET; electrostatic devices; nanowires; numerical analysis; semiconductor device models; silicon-on-insulator; 2D tunneling effects; III-V p-TFET; cylindrical nanowire devices; degeneracy effects; double gate devices; electrostatic modeling; excessive source doping; low density-of-states materials; multigate TFET; multigate lateral tunneling transistors; nonabrupt junctions; numerical simulations; pseudo-2-D analytical models; seminal analytical treatment; silicon-on-insulator; Approximation methods; Doping; Electric potential; Logic gates; Mathematical model; Semiconductor process modeling; Tunneling; Analytical modeling; Poisson equation; double-gate (DG); multigate; nanowire (NW); silicon-on-insulator (SOI); tunneling field-effect transistor (TFET);
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2013.2272040
  • Filename
    6562768