Title :
Yield Model for Planning and Controlling the Manufacture of VLSI Memory Chips
Author :
Stapper, Charles H.
Author_Institution :
IBM General Technology Division Essex Essex Junction, Vermont 05452, U.S.A.
Abstract :
The subject of this paper is a yield model that has been used for optimizing chip productivity, planning, manufacturing, learning, and controlling the manufacture of VLSI memory chips. Examples of the use of this model and results are described.
Keywords :
Circuit faults; Contact resistance; Productivity; Pulp manufacturing; Random access memory; Semiconductor device modeling; Statistics; Technology planning; Very large scale integration; Virtual manufacturing;
Conference_Titel :
VLSI Technology, 1985. Digest of Technical Papers. Symposium on
Conference_Location :
Kobe, Japan
Print_ISBN :
4-930813-09-3
