DocumentCode
472629
Title
A Novel Approach to Reduce Damages in Gate Oxides Induced by Bias Sputtered Sio2 Deposition
Author
Hazuki, Y. ; Moriya, T.
Author_Institution
Toshiba Corporation, VLSI Research Center 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki 210, Japan
fYear
1985
fDate
14-16 May 1985
Firstpage
20
Lastpage
21
Abstract
Vth shifts of MOS transistors, on which the conventinal bias sputtered SiO2 films were deposited, became negligibly small after annealing at 450°C. But, ¿Vth´s by bias stress test were larger than those of reference samples, since damages consisted of neutral traps were induced in gate oxides of MOS transistors in the bias sputtered SiO2 deposition which result from the effect of secondary X-ray, generated by electrons which come from the target, on gate oxides. The grid electrode was used for decrease of electrons from the target to the substrate. This novel approach reduced damage introduction to the degree acceptable in practical use.
Keywords
Annealing; Cathodes; Electrodes; Electrons; Insulation; MOS devices; MOSFETs; Stress; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1985. Digest of Technical Papers. Symposium on
Conference_Location
Kobe, Japan
Print_ISBN
4-930813-09-3
Type
conf
Filename
4480283
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