Fabrication Technologies for Multilayer CMOS Device

Fundamental technologies required to fabricate a multilayer device were studied. Dual laser beam recrystallization method was developed to obtain homogeneous crystal quality Si islands through 5 cm × 5 cm area. The planarized heat sink (PHS) structure was proposed to stack the laser recrystallized Si islands layer on the top of the lower IC. Nondoped MoSi2 was utilized as a buried interconnection to be stacking CMOS IC in an each layer, instead of a conventional A1 interconnection of CMOS. Using these fundamental process technologies for the multilayer device, the 3 level device having the different function in each active layer was fabricated and was successfully operated.