A Sub-Hundred NSEC DRAM Using the Taper Isolated Dynamic RAM Cell

Author

Chatterjee, P.K. ; Leiss, J.E. ; Holloway, T.C.

Author_Institution

VLSI Laboratory Texas Instruments Incorporated Dallas, Texas

fYear

1981

fDate

9-11 Sept. 1981

Firstpage

Lastpage

Keywords

Circuits; Clocks; DRAM chips; Decoding; Laboratories; Random access memory; Signal design; Transconductance; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1981. Digest of Technical Papers. Symposium on

Conference_Location

Maui, HI, USA

Type

Filename

4480520

Link To Document