Concurrent 10.5/25 GHz CMOS power amplifier with harmonics and inter-modulation products suppression

A concurrent 10.5/25 GHz power amplifier (PA) is designed and implemented in a 0.18 μm CMOS technology. This PA employs dual-band matching networks that can suppress harmonics, inter-modulation products, and out-of-band signals so as to improve linearity performances. Moreover, the driver stage of the PA utilises a current-reused topology which increases the gain without increase of the power dissipation. The chip size of the PA is 0.95 × 0.91 mm² including testing pads, and its power consumption is 150 mW. The PA exhibits a measured gain of 15.2 and 6.8 dB, output P_1dB of 10.5 and 9 dBm, P_out,max of 11.4 and 10 dBm and power added efficiency of 9 and 4.8% at 10.5 (f₁) and 25 GHz (f₂), respectively. The measured rejection of signals at 4 GHz (f₂-2f₁), 14.5 GHz (f₂ - f₁) and 21 GHz (2f₁) is 43, 16.5 and 10.8 dB, respectively.