Checking properties of PLL designs using run-time verification

Due to challenges associated with its verification process, analog and mixed signal designs like PLLs require a considerable portion of the total design time. In this paper, we propose a run-time verification approach for PLL designs. The essence of this approach is to monitor properties of interest by timed automata integrated within an automatic stimulus generation framework. The objective is to guide simulation by an appropriate simulation trace in order to quickly detect errors by the property monitor.