Rapid application specific floating-point unit generation with bit-alignment

While ASIPs have allowed designers to create processors with custom instructions to target specific applications, floating point units are still instantiated as fixed general-purpose units, which wastes area if not fully utilized. Therefore, there is a need for custom FPUs for embedded systems. The creation of a custom FPU requires the selection of a subset of the full floating-point instruction set and the implementation of this subset in hardware, such that the runtime of the application is minimized. To minimize area, it is desirable to merge the datapaths for each of the floating-point operations, so that redundant hardware is minimized. Floating-point datapaths are complex and contain components with varying bit-widths, so sharing components of different bit-widths is necessary. However, this introduces the problem of bit-alignment, which involves determining how smaller resources should be aligned within larger resources when merged. This is a problem that has been largely neglected in previous work. Thus, this paper presents a novel algorithm for solving the bit-alignment problem, which neatly integrates into the datapath merging process. By solving this bit-alignment problem, automatic datapath merging can be made available for FPU generation. To explore the trade-offs between area and performance, a rapid design space exploration was performed to determine which FP operations should be implemented in hardware rather than emulated. Our results show that more floating-point hardware does not necessarily equate to lower run-time if the additional hardware increases delay. We found that bit-alignment reduced area by an average of 22.5% in our benchmarks, compared to an average of 14.1% without bit-alignment.