Translation of an existing VMM-based SystemVerilog testbench to OVM

Many features built into the SystemVerilog language make it an extremely effective high-level verification language. Using class libraries with SystemVerilog can take this a step further by enhancing productivity, and enabling better, more efficient reuse between engineers and between projects. The verification methodology manual (VMM) class library was one of the first SystemVerilog class libraries available, and has been widely adopted. The open verification methodology (OVM) class library has just become available, and while it is similar to VMM in many respects, there are also some important differences. This paper describe the process of converting an existing testbench based on VMM class libraries, to one based on OVM class libraries. The VMM testbench selected for the conversion to OVM was developed for the verification of a custom memory controller for a general purpose DSP SOC. The EBIU (external bus interface unit) is complex enough to require a non-trivial testbench, and the large number of system busses makes it an interesting candidate for a randomized SystemVerilog testbench approach.This paper begin by describing the conversion process of the basic testbench components, including transaction classes and bus functional models. The next step is converting the testbench environment, and adding the extra layers of abstraction which are part of the OVM methodology. Finally, the conversion of the actual tests is described, including the configuration phase, and the transaction generation. The paper conclude by summarizing the similarities and differences between the two approaches, and highlight which aspects of the conversion were straight forward, and which aspects required more attention.