The mixed signal optimum energy point: Voltage and parallelism

An energy optimization is proposed that addresses the non-trivial digital contribution to power and impact on performance in high-speed mixed-signal circuits. Parallel energy and behavioral models are used to quantify architectural tradeoffs across the analog/digital boundary. An interleaved ADC is optimized as a case study to demonstrate this approach. The chosen operating point of 36 channels and 700 mV operation gives a 3x improvement in energy compared to the seed of the model. The model matches closely the measured results of an ADC testchip implemented in a 65 nm CMOS process.