Tera-scale computing and interconnect challenges

Future CPU directions are increasingly emphasizing parallel compute platforms which are critically dependent upon upon greater core to core communication as well as generally stressing the overall memory and storage interconnect hierarchy to a much greater degree than extrapolations of past platform needs. Performance is critically dependent upon memory bandwidth and latency but must be moderated with power and cost considerations. 3D stacking of CPU´s and memory (i.e. a last level cache) is a potential solution that provides the necessary bandwidth within a reasonable power envelope.