A new digital multiplier/divider architecture, via hybrid analog-digital processing

Digital multiplying and dividing are time consumer tasks if are done via software. To speed up, the processor special hardware may be developed. Digital multipliers/dividers designed by digital circuits are too huge and complex in a system point of view and each of them need own hardware and so they’re occupying large amount of die. In this paper a digital multiplier/divider which uses hybrid processesμ of analog and digital circuits will be introduced. This multiplier/divider is very simple and uses the same device for both operations, so it’ll occupy the die, less. The idea will be developed in system level and some comparisons with similar devices will be done at this level.