Address generator realization using completely-specified Boolean functions

We are proposing a cost-efficient realization scheme for completely-specified logic functions characterized by a huge disproportion. The functions described contain millions of input words but only few of them can give us information. An appropriate method of logic synthesis for identifying mentioned vectors (registered vectors) has been developed. In this method logic functions are implemented using both embedded memory blocks and LUT-based programmable logic blocks available in today’s FPGAs. The paper presents the results of our research. In comparison with the classical logic synthesis methods and other dedicated methods we have obtained extremely encouraging results: with a comparable number of EMBs, the number of logic cells has been reduced by 95%. The investigation has been implemented using Altera’s Stratix devices.