A parallel Circular-Scan architecture using multiple-hot decoder

This paper presents a new Circular-Scan architecture that makes it possible to select several scan chains in parallel. The basic idea of Circular-Scan architecture is use of the captured response of the previously applied pattern as a template for the next pattern while allowing the full observation of the captured response. In comparison with original architecture which it is possible to select only one scan chain in each time, the parallel updating of conflict bits results in reduction in test data volume and test application time. The proposed architecture relies on Circular-scan architecture and multiple-hot decoders. Experimental results show an average improvement of 26% in test data volume and test application time in 5 largest ISCAS’89 circuits.