DocumentCode
475492
Title
VHDL implementation of the lane detection algorithm
Author
Pankiewicz, P. ; Powiertowski, W. ; Roszak, G.
Author_Institution
Pozna¿ University of Technology, POLAND
fYear
2008
fDate
19-21 June 2008
Firstpage
581
Lastpage
584
Abstract
The aim of the following paper is to present a proposed VHDL implementation of a vision based lane detection algorithm. During the research several approaches to edge and line detection were analysed, which resulted in an optimal combination. The proposed algorithm is based on the Canny edge detector and the linear Hough transform for line detection. The system had been pre-developed using the Matlab environment, followed by a synthesizable hardware description using VHDL. A wide range of testing procedures for structural and behavioural verification was designed. The presented evaluation of both the hardware and software simulations, as well as the synthesis results proved high capabilities of the designed architecture.
Keywords
Computer architecture; Detection algorithms; Detectors; Equations; Field programmable gate arrays; Hardware; Image edge detection; Image processing; Roads; Transforms; Canny edge detection; FPGA; Hough transform; Lane detection; PowerPC; VHDL;
fLanguage
English
Publisher
iet
Conference_Titel
Mixed Design of Integrated Circuits and Systems, 2008. MIXDES 2008. 15th International Conference on
Conference_Location
Poznan, Poland
Print_ISBN
978-83-922632-7-2
Electronic_ISBN
978-83-922632-8-9
Type
conf
Filename
4600988
Link To Document