A new fabric of reconfigurable FFT processor for high-speed and low-cost system

Author

Liu, Huan ; Pan, Wei ; Lin, Shui-sheng

Author_Institution

Sch. of Commun. & Inf. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu

Volume

6

fYear

2008

fDate

12-15 July 2008

Firstpage

3525

Lastpage

3529

Abstract

A high-speed reconfigurable FFT architecture based on FPGA is proposed in this paper. The system can be configured as 32, 64,128, 256, 512 and 1024-point FFT using simplified method to control. It has been synthesized in Xilinx Virtex2p FPGA and post-simulated. Compared with Xilinx FFT IP Core with the same function, this FFT fabric proposed has saved almost 8%~9% (equivalent gates) in resources consumption while increased nearly 6%~25% in clock frequency and decreased 56~116 cycles of delays from first input data to the first result data, indicating high computing efficiency. On the other hand, power consumption is also slightly fewer than the IP Corepsilas. The fabric we presented in this paper is suitable for use in digital signal process with high-speed and low-cost.

Keywords

fast Fourier transforms; field programmable gate arrays; microprocessor chips; reconfigurable architectures; Xilinx Virtex2p FPGA; fast Fourier transform; field programmable gate arrays; reconfigurable FFT processor; Application specific integrated circuits; Clocks; Cybernetics; Digital signal processing chips; Fabrics; Field programmable gate arrays; Frequency estimation; Machine learning; Signal processing; Signal processing algorithms; FFT; FPGA; Reconfigurable;

fLanguage

English

Publisher

ieee

Conference_Titel

Machine Learning and Cybernetics, 2008 International Conference on

Conference_Location

Kunming

Print_ISBN

978-1-4244-2095-7

Electronic_ISBN

978-1-4244-2096-4

Type

conf

DOI

10.1109/ICMLC.2008.4621014

Filename

4621014