Carbon Nanotube Based 3-D Interconnects - A Reality or a Distant Dream

A 3D IC is a chip having multiple tiers of stacked dies. The vertically stacked dies are electrically connected through 3D/vertical interconnects or popularly known as through-silicon-vias (TSVs). Development of a reliable 3D integrated system is largely dependent on the choice of filler material used in the TSV. Although, several researchers and fabrication houses have demonstrated the usage of copper as filler material, but, over the time it would suffer due to the rapid increase in resistivity under the combined effects of enhanced grain boundary scattering, surface scattering and the presence of a highly diffusive barrier layer. However, these limitations can be overcome by CNTs that exhibit higher mechanical and thermal stability, higher conductivity and larger current carrying capability. Moreover, a bundle of CNT conducts current parallely that drastically reduces the resistive parasitic and thereby propagation delay. Thus, bundled CNTs can be predicted as one of the potential candidates for future high-speed TSVs. However, the CNT growth temperature is greater than 600?A 3D IC is a chip having multiple tiers of stacked dies. The vertically stacked dies are electrically connected through 3D/vertical interconnects or popularly known as through-silicon-vias (TSVs). Development of a reliable 3D integrated system is largely dependent on the choice of filler material used in the TSV. Although, several researchers and fabrication houses have demonstrated the usage of copper as filler material, but, over the time it would suffer due to the rapid increase in resistivity under the combined effects of enhanced grain boundary scattering, surface scattering and the presence of a highly diffusive barrier layer. However, these limitations can be overcome by CNTs that exhibit higher mechanical and thermal stability, higher conductivity and larger current carrying capability. Moreover, a bundle of CNT conducts current parallely that drastically reduces the resistive parasit- c and thereby propagation delay. Thus, bundled CNTs can be predicted as one of the potential candidates for future high-speed TSVs. However, the CNT growth temperature is greater than 600°C that is unfortunately incompatible with CMOS devices and many other temperature-sensitive materials, therefore, the manufacturing of CNTs largely depends on the success of fabrication houses.C that is unfortunately incompatible with CMOS devices and many other temperature-sensitive materials, therefore, the manufacturing of CNTs largely depends on the success of fabrication houses.