Energy Efficient Register File Window Access in SPARC Architecture

As power dissipation of the register file in modern processor designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing the SPARC windowed register file power based on the operation of the Register File Inspector added in the decode stage of the pipeline. The power savings show that, when the size of the Register File Inspector is properly fixed, the average saving on the energy consumption of the windowed register file could be up to 74% compared with the traditional register file control scheme.