GEMI: A High Performance and High Flexibility Memory Interface Architecture for Complex Embedded SOC

Two of the most significant factors in the success of todaypsilas system-on-chip (SoC) designs are the ability to deliver efficient access to off-chip high speed memory and the ability to be compatible with several different interface-timings of several different sorts of memories. And the scheduling scheme of data streams for multi-master and multi-outstanding requests situation in complex SoC should be considered carefully, too. This paper introduces a novel general external memory interface (GEMI) architecture for the high performance and high flexibility memory interface. Several techniques and methods, i.e. data and command buffers based on asynchronous FIFO, optimized bank management, multi-port access scheduler, request reorder unit, are proposed in this paper for fulfilling the requirements mentioned above. Some techniques are specially proposed for data streams scheduling in complex SoC. At the end of the paper, the simulation and tape-out results are provided. The whole implementation of architecture is proven to be not only functional and efficient, but also flexible and reusable by simulation and silicon verification.