Mitigating Multi-Bit-Upset With Well-Slits in 28 nm Multi-Bit-Latch

This paper proposes a technique that mitigates multi-bit-upset (MBU) in multi-bit-latch (MBL) without performance degradation by applying well-slits. The area overhead in an MBL macro for processor design, which includes a clock buffer and a checker, is only 5.4% in a 28 nm technology. Sixty-hour accelerated neutron irradiation test observed no MBUs in the MBL with well-slits. The proposed mitigation technique achieved excellent robustness against MBU without any increase in SBU rate. The MBL with the proposed mitigation technique helps improve reliability of electronic devices.