Title :
A SOC Design for AVS Video Decoding
Author_Institution :
Chinese-German Coll., Tongji Univ., Shanghai
Abstract :
In this paper, a decoding IP core for audio video coding standard (AVS) was designed, which can support AVS JiZhun profile High-Definition video bit stream real-time decoding. System composing of the SOC design and control flow of decoding was described in detail. Logical and feasible division between software and hardware was presented on the basis of sufficient validity check. C reference model for whole decoder was proposed as well, which was used to verify the decoding algorithm. Clear and smooth picture can be output both on the C model environment and SOC platform. Besides, system clock supply for IP core and sub-modules inside can be halted whenever necessary, so that power consumption for the whole system was also reduced. Though designed for AVS originally, the proposed architecture can be adapted to other coding standards easily.
Keywords :
C language; audio coding; code standards; decoding; hardware-software codesign; system-on-chip; video coding; AVS video decoding; C reference model; IP core decoding; SOC design; audio video coding standard; high-definition video bit stream real-time decoding; power consumption; software-hardware division; system clock supply; Computational intelligence; Conferences; Costs; Decoding; Hardware; High definition video; Power system modeling; Streaming media; Video coding; Video compression; AVS; C model; IP core; SOC;
Conference_Titel :
Computational Intelligence and Industrial Application, 2008. PACIIA '08. Pacific-Asia Workshop on
Conference_Location :
Wuhan
Print_ISBN :
978-0-7695-3490-9
DOI :
10.1109/PACIIA.2008.63