• DocumentCode
    483384
  • Title

    CDM analysis on 65nm CMOS: Pitfalls when correlating results between IO test chips and product level

  • Author

    Suzuki, Teruo ; Hashimoto, Kenji ; Isomura, Nobuyoshi ; Yokota, Noboru ; Marichal, Olivier ; Sorgeloos, Bart ; Van Camp, Benjamin ; Keppens, Bart

  • Author_Institution
    Macro Dev. Dept., Fujitsu VLSI Ltd., Kasugai, Japan
  • fYear
    2008
  • fDate
    7-11 Sept. 2008
  • Firstpage
    325
  • Lastpage
    331
  • Abstract
    Unlike HBM and MM, CDM robustness is highly dependent on IC layout and packaging. Therefore, IC companies mimic IC IO rings on IO-TEG test chips to select the most appropriate CDM protection concepts (correlation from IO-TEG to final IC¿s). This publication highlights pitfalls for this approach. Ensuring consistent substrate and Vss connections drastically improve the correlation.
  • Keywords
    CMOS integrated circuits; integrated circuit layout; integrated circuit modelling; integrated circuit packaging; integrated circuit testing; CDM analysis; CMOS; IC layout; IC packaging; IO test chips; pitfalls; product level; size 65 nm; Application specific integrated circuits; Earth Observing System; Electrostatic discharge; Europe; Microelectronics; Packaging; Protection; Robustness; Testing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th
  • Conference_Location
    Tucson, AZ
  • Print_ISBN
    978-1-58537-146-4
  • Electronic_ISBN
    978-1-58537-147-1
  • Type

    conf

  • Filename
    4772151
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=483384