The development of advanced verification environments using System Verilog

This paper describes a System Verilog Verification Methodology Manual (VMM) test bench architecture that is structured to gain maximum efficiency from both constrained random and directed test case development. We specify how a novel form of directed traffic can be implemented in parallel to a complete random traffic generator inside a reusable directory structure which takes full advantage of coverage and assertion techniques. The paper uses an IEEE-754 compliant Floating-Point adder model as part of a case study that illustrates a complete set of results from using this test bench solution.