A novel design of low power RFID tag interface circuit

This paper describes a novel architecture of interface circuit of passive tags based on ISO/IEC 15693 standard. Many low power optimization techniques of the interface circuit are proposed. The simulation results show that the design of RF interface circuit is low power, high performance and highly reliable, and meets the tag design requirement. It has been applied to a passive tag design, which was fabricated successfully based on 0.35 mum CMOS technology.