Compact algorithmic time-to-digital converter

Time-to-digital converters (TDCs) are an important circuit block in time-of-flight sensors, fluorescence lifetime sensors, and self-calibrating digital circuits. Fine-resolution TDCs are usually built with chains of delay elements, but this architecture requires large area, conversion time, and power consumption. A novel compact TDC architecture based on the cyclic comparison algorithm is presented, which implemented and tested in the TSMC, 0.35 μm process within a 200 × 200 μm area is demonstrated that the proposed TDC achieves a conversion rate of 10 ns/bit and sub-picosecond resolution. The measured power is 0.7 mW, taking 100 ns for each bit.