Design of high-performance unified motion estimation IP for H.264/MPEG-4 video CODEC

Motion estimation for H.264/MPEG-4 video CODEC is very complex and requires a huge amount of computational effors because it uses multiple reference frames and variable block sizes. This paper describes the architecture and design of high-performance unified motion estimation IP based on fast algorithms for multiple reference frame selection, block matching with variable search window, block mode decision, and motion vector estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The resultant circuit consists of 77,600 logic gates and 4 32times8times32-bit dual-port SRAM´s. It has the maximum operating frequency of 161MHz and can process up to 51 D1 (720times480) color image frames per second.