DocumentCode
492713
Title
A design of full-CMOS VDSL2 receiver in 0.25μm CMOS process
Author
Kim, Youngshin ; Pu, Young-Gun ; Kim, Tai-Young ; Cho, HooHyun ; Ko, DongHyun ; Lee, Kang-Yoon ; Kim, Tai-Hyung ; Lee, Joon-Beom
Author_Institution
Dept. of Electron. Eng., Konkuk Univ., Seoul
Volume
01
fYear
2008
fDate
24-25 Nov. 2008
Abstract
This paper presents a full-CMOS single-chip Receiver PHY IC for VDSL2 systems. In the receiver part, the low-pass filter, VGA, and ADC is designed to have a wide dynamic range and gain control range because the signal from the VDSL2 line is variable depending on the distance. This chip is fabricated with 0.25 mum CMOS technology, and the die area is 5 mm times 5 mm. The power consumption is 250 mW at 2.5 V supply voltage in Rx mode.
Keywords
CMOS integrated circuits; analogue-digital conversion; digital subscriber lines; gain control; low-pass filters; receivers; ADC; CMOS process; VGA; full-CMOS single-chip VDSL2 receiver; gain control range; low-pass filter; power 250 mW; size 0.25 mum; voltage 2.5 V; CMOS process; CMOS technology; Dynamic range; Gain control; Low pass filters; Modems; Physical layer; Resistors; Signal design; Switches; ADC; CMOS; LPF; Receiver; VDSL2; VGA;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference, 2008. ISOCC '08. International
Conference_Location
Busan
Print_ISBN
978-1-4244-2598-3
Electronic_ISBN
978-1-4244-2599-0
Type
conf
DOI
10.1109/SOCDC.2008.4815640
Filename
4815640
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