A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort

Author

Lee, Seungwon ; Yoo, Jae-Wook ; Kang, Jin-Ku

Author_Institution

Dept. of Electron. Eng., INHA Univ., Incheon

Volume

02

fYear

2008

fDate

24-25 Nov. 2008

Abstract

This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7 Gbps and 1.62 Gbps for DisplayPort sink device. This CDR uses the half-rate linear phase detector (PD). A voltage-controlled oscillator (VCO) is proposed to change the operating frequency of half-rate clock with a ldquoModerdquo switch control. This work is implemented 0.18 mum CMOS process. The device exhibits peak-to-peak jitters of 12 ps and 14 ps in the recovered clock with random data inputs. The power dissipation is 81 mW from a 1.8 V supply.

Keywords

CMOS integrated circuits; clock and data recovery circuits; display devices; heat sinks; voltage-controlled oscillators; CMOS process; DisplayPort sink device; Mode switch control; bit rate 1.62 Gbit/s; bit rate 2.7 Gbit/s; clock-and-data recovery circuit; dual-mode clock; half-rate clock; half-rate linear phase detector; peak-to-peak jitters; power dissipation; random data inputs; size 0.18 mum; voltage 1.8 V; voltage-controlled oscillator; CMOS process; Circuits; Clocks; Detectors; Frequency; Jitter; Phase detection; Switches; Voltage control; Voltage-controlled oscillators; DisplayPort; clock and data recovery (CDR); half-rate phase detector (PD); voltage-controlled oscillator (VCO);

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference, 2008. ISOCC '08. International

Conference_Location

Busan

Print_ISBN

978-1-4244-2598-3

Electronic_ISBN

978-1-4244-2599-0

Type

conf

DOI

10.1109/SOCDC.2008.4815672

Filename

4815672