DocumentCode
492872
Title
SoC functional intellectual property diagnosis
Author
Sushanov, Aleksey ; Varetza, Vitaliy ; Dementyev, Sergey ; Vasilenko, Vasilina
Author_Institution
Comput. Eng. Fac., Kharkov Nat. Univ. of Radioelectron., Kharkov, Ukraine
fYear
2009
fDate
24-28 Feb. 2009
Firstpage
263
Lastpage
266
Abstract
The diagnosis methods of digital system on a chip, based on the disjunctive normal form, which is represented by fault coverage matrix of test sequences are proposed. The method is focused on the built-in-service functionality, presented by F-IP modules. Strategy of check-points choice which is directed on search of multiple faults in the system functionality in real time is considered.
Keywords
matrix algebra; system-on-chip; F-IP modules; SoC functional intellectual property diagnosis; built-in-service functionality; check-points choice; digital system on a chip; disjunctive normal form; fault coverage matrix; test sequences; Digital systems; Energy consumption; Fault diagnosis; Hardware; Intellectual property; Phase measurement; Real time systems; Registers; System testing; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
CAD Systems in Microelectronics, 2009. CADSM 2009. 10th International Conference - The Experience of Designing and Application of
Conference_Location
Lviv-Polyana
Print_ISBN
978-966-2191-05-9
Type
conf
Filename
4839826
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