Scaling the Performance of Tiled Processor Architectures with On-Chip-Network Topology

The trend in wire delays due to resistance is becoming a significant problem for microprocessor designers, forcing radically new tiled microprocessor architecture designs. This type of architecture will necessarily incorporate on-chip networks topology. This paper examines a few of the possible on-chip network topology in the context of tiled processor architectures. Firstly, by investigating some proposed tiled processor architecture, we observe that the on chip network interconnecting is the critical design point in the architectures. After that, we discuss the candidate topologies of on-chip network topology that satisfy these properties. Finally, a detailed experimental evaluation of these networks topology is presented to highlight the scalability and performance of these tiled processor architectures. Results show that we can achieve performance improvement by modifying basic mesh appropriately according to the granularity of the tile within technology restrictions.