A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications

Author

Park, C.S. ; Hussain, M.M. ; Huang, J. ; Park, C. ; Tateiwa, K. ; Young, C. ; Park, H.K. ; Cruz, M. ; Gilmer, D. ; Rader, K. ; Price, J. ; Lysaght, P. ; Heh, D. ; Bersuker, G. ; Kirsch, P.D. ; Tseng, H.-H. ; Jammy, R.

Author_Institution

SEMATECH, Austin, TX, USA

fYear

2009

fDate

16-18 June 2009

Firstpage

208

Lastpage

209

Abstract

This paper reports on a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32 nm LSTP applications: V_t < plusmn 0.45 V (at L_g = 60 nm) at EOT les 1.4 nm, with 10⁵ times J_g reduction compared to SiO₂. This scheme integrates several simplifications and improvements for the first time: single metal gate material, single channel material, dual selective LaO_x / AlO_x cap removal without lithographic overlay tolerances issues and optimized HfSiON for LSTP leakage targets.

Keywords

CMOS integrated circuits; hafnium compounds; high-k dielectric thin films; low-power electronics; silicon compounds; CMOS technology; HfSiON; SiO₂; gate-first integration option; high-k gates; lithographic overlay tolerance; low standby power; metal gate; Amorphous materials; CMOS process; CMOS technology; Dielectric losses; High K dielectric materials; High-K gate dielectrics; Inorganic materials; MOS devices; Manufacturing; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2009 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-3308-7

Type

conf

Filename

5200601