DocumentCode
497187
Title
Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm application
Author
Huang, J. ; Heh, D. ; Sivasubramani, P. ; Kirsch, P.D. ; Bersuker, G. ; Gilmer, D.C. ; Quevedo-Lopez, M.A. ; Hussain, M.M. ; Majhi, P. ; Lysaght, P. ; Park, H. ; Goel, N. ; Young, C. ; Park, C.S. ; Park, C. ; Cruz, M. ; Diaz, V. ; Hung, P.Y. ; Price, J. ;
Author_Institution
SEMATECH, Austin, TX, USA
fYear
2009
fDate
16-18 June 2009
Firstpage
34
Lastpage
35
Abstract
Gate first 0.59 nm EOT HfOx/metal gate stacks for 16 nm node application are demonstrated for the first time. By controlling O during HfOx deposition, ldquozerordquo low-k SiOx interface (ZIL) forms despite a 1020degC activation anneal. This 0.59 nm EOT is a 30% improvement over a state of the art 32 nm HK/MG technology. We compare and demonstrate for the first time the improved scalability of ZIL HfOx vs. exotic higher-k. Transistors made with ZIL HfOx show good interfaces (SS=70-80 mV/dec, Nit = 5 times 1010/cm2) and performance (10% Ion-Ioff boost vs. EOT = 0.95 nm), despite mobility loss. Factors contributing to mobility loss in ZIL HfOx are discussed.
Keywords
annealing; hafnium compounds; insulated gate field effect transistors; nanotechnology; activation anneal; high k-metal gate stacks; mobility loss; size 0.59 nm; temperature 1020 degC; transistors; zero low-k SiOx interface; Annealing; Bismuth; CMOS technology; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Jamming; Oxidation; Scalability; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2009 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-3308-7
Type
conf
Filename
5200624
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