Design and FPGA implementation of fast variable length coder for video encoder

Author

Venugopal, N. ; Ramachandran, S. ; Adiga, B.S.

Author_Institution

MGR Univ., Chennai, India

fYear

2009

fDate

4-6 June 2009

Firstpage

1

Lastpage

6

Abstract

This paper proposes a novel implementation of one of the core processors of a video encoder, the variable length coder using single FPGA. The processor is implemented on a Xilinx Virtex - II Pro XUPVP30 FPGA. The gate count of the implementation is approximately 690,000 including an output FIFO of size 128 Kb. It can process 1600 times 1200 pixels color motion pictures in 4:2:0 format at over 30 frames per second as per MPEG-2 standard. The compression effected is about 38 and the reconstructed picture is of good quality with a PSNR values of 33 dB or more.

Keywords

data compression; discrete cosine transforms; field programmable gate arrays; image resolution; microprocessor chips; video coding; FPGA implementation; MPEG-2 standard; Xilinx Virtex-II Pro XUPVP30 FPGA; color motion pictures; core processors; discrete cosine transform; fast variable length coder; gate count; output FIFO; video compression; video encoder; Color; Digital video broadcasting; Discrete cosine transforms; Field programmable gate arrays; Motion pictures; Quantization; Streaming media; Transform coding; Video codecs; Video compression; DCTQ; Encoder; FIFO; RLE; VLC;

fLanguage

English

Publisher

ieee

Conference_Titel

Control, Automation, Communication and Energy Conservation, 2009. INCACEC 2009. 2009 International Conference on

Conference_Location

Perundurai, Tamilnadu

Print_ISBN

978-1-4244-4789-3

Type

conf

Filename

5204485