32-Mb 2T1R SPRAM with localized bi-directional write driver and ‘1’/‘0’ dual-array equalized reference cell

Author

Takemura, R. ; Kawahara, T. ; Miura, K. ; Yamamoto, H. ; Hayakawa, J. ; Matsuzaki, N. ; Ono, K. ; Yamanouchi, M. ; Ito, K. ; Takahashi, H. ; Ikeda, S. ; Hasegawa, H. ; Matsuoka, H. ; Ohno, H.

Author_Institution

Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo, Japan

fYear

2009

fDate

16-18 June 2009

Firstpage

84

Lastpage

85

Abstract

A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200 nm tunnel magnetoresistive device element. This chip features three circuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large writing current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing writing current, and 3) a ‘1’/‘0’ dual-array equalized reference cell for stable read operation.

Keywords

Bidirectional control; Capacitance; Laboratories; Large-scale systems; Nanoelectronics; Read-write memory; Temperature; Tunneling magnetoresistance; Voltage; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2009 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

978-1-4244-3307-0

Electronic_ISBN

978-4-86348-001-8

Type

conf

Filename

5205284