• DocumentCode
    497945
  • Title

    A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

  • Author

    Kohama, Yoshinori ; Sugimori, Yasufumi ; Saito, Shotaro ; Hasegawa, Yohei ; Sano, Toru ; Kasuga, Kazutaka ; Yoshida, Yoichi ; Niitsu, Kiichi ; Miura, Noriyuki ; Amano, Hideharu ; Kuroda, Tadahiro

  • Author_Institution
    Department of Electronic Engineering and Electronics, Keio University, Yokohama, Japan
  • fYear
    2009
  • fDate
    16-18 June 2009
  • Firstpage
    94
  • Lastpage
    95
  • Abstract
    This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031 mm2. Average execution time is reduced to 31% compared to that using one chip.
  • Keywords
    Stacking;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2009 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    978-1-4244-3307-0
  • Electronic_ISBN
    978-4-86348-001-8
  • Type

    conf

  • Filename
    5205288
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=497945