DocumentCode
497997
Title
A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective
Author
Zhou, Dajiang ; You, Zongyuan ; Zhu, Jiayi ; Kong, Ji ; Hong, Yu ; Chen, Xianmin ; He, Xuewen ; Xu, Chen ; Zhang, Hang ; Zhou, Jinjia ; Deng, Ning ; Liu, Peilin ; Goto, Satoshi
Author_Institution
Graduate School of Information, Production and Systems, Waseda University, 2-7 Hibikino, 808-0135, Japan
fYear
2009
fDate
16-18 June 2009
Firstpage
262
Lastpage
263
Abstract
In this paper, we present a video decoder chip for H.264/AVC high profile, MPEG-1/2 main profile and AVS Jprofile, which is capable of 60fps 1080p decoding at 200MHz. By applying a dedicated DRAM sub-system and a 2-D cache architecture, 50% of pins for DRAM connection and 36% of power consumption are saved, compared to state-of-the-art work in a system perspective. Meanwhile, 38% of gate count is reduced by applying resource sharing architectures between the 3 supported video formats.
Keywords
Bandwidth; Buffer storage; Costs; Decoding; Displays; Packaging; Pins; Random access memory; Resource management; Video sharing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2009 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
978-1-4244-3307-0
Electronic_ISBN
978-4-86348-001-8
Type
conf
Filename
5205354
Link To Document