• DocumentCode
    498048
  • Title

    A 31ns random cycle VCAT-based 4F2 DRAM with enhanced cell efficiency

  • Author

    Song, Ki-Whan ; Kim, Jin-Young ; Kim, Huijung ; Chung, Hyun-Woo ; Kim, Hyungi ; Kim, Kanguk ; Park, Hwan-Wook ; Kang, Hyun Chul ; Kim, Sua ; Tak, Nam-kyun ; Park, Dukha ; Kim, Woo-Seop ; Lee, Yeong-Taek ; Oh, Yong Chul ; Jin, Gyo-Young ; Yoo, Jeihwan ; Oh

  • Author_Institution
    ATD and ATD 1, Korea
  • fYear
    2009
  • fDate
    16-18 June 2009
  • Firstpage
    132
  • Lastpage
    133
  • Abstract
    This paper reports a functional 4F2 DRAM based on a vertical-channel-access-transistor (VCAT). A new core design methodology is applied to accommodate 4F2 cell array, achieving both high performance and small area. The 88Kb DRAM array is fabricated in a 50Mb test chip at 80nm design rule and the measured random cycle time (tRC) and read latency (tRCD) is 31ns and 8ns, respectively. The core array size is reduced by 29% compared to conventional 6F2 DRAM.
  • Keywords
    CMOS technology; Circuits; Design methodology; MIM capacitors; Manufacturing; Random access memory; Research and development; Semiconductor device measurement; Testing; Time measurement; 4F2; DRAM; VCAT;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2009 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    978-1-4244-3307-0
  • Electronic_ISBN
    978-4-86348-001-8
  • Type

    conf

  • Filename
    5205418
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=498048