DocumentCode
500856
Title
Context-sensitive timing analysis of Esterel programs
Author
Ju, Lei ; Huynh, Bach Khoa ; Chakraborty, Samarjit ; Roychoudhury, Abhik
Author_Institution
Dept. of Comput. Sci., Nat. Univ. of Singapore, Singapore, Singapore
fYear
2009
fDate
26-31 July 2009
Firstpage
870
Lastpage
873
Abstract
Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software - e.g., into sequential C code - very conservative estimation techniques have been used, where the focus has only been on obtaining safe timing estimates and not on the cost of the implementation. While this was acceptable in avionics, efficient implementations and hence tight timing estimates are needed in more cost-sensitive application domains. Lately, a number of advances in worst-case execution time (WCET) analysis techniques, coupled with the growing use of software in domains such as automotives, have led to a considerable interest in timing analysis of code generated from Esterel specifications. In this paper we propose techniques to obtain tight estimates on the processing time of input events by sequential C code generated from Esterel programs. Execution of an Esterel program - as in all other synchronous languages - is logically made up of a sequence of clock ticks. In reality, they take non-zero time which depends on the generated C code as well as the underlying hardware platform on which this code is executed. Apart from exploiting the specific structure of this C code to obtain tight WCET estimates, we capture program-level contexts across ticks in order to obtain tight estimates on response times of events whose processing spans across multiple clock ticks. Such tighter estimates immediately translate into more cost-effective implementations. Our experimental results with realistic case studies show 30% reduction in timing estimates when program level context information is taken into account.
Keywords
C language; sequential codes; software performance evaluation; timing; Esterel program; Esterel specification; WCET analysis; clock tick; context-sensitive timing analysis; cost-sensitive application; program level context information; program-level context; response time; sequential C code; synchronous language; timing analysis; timing estimate; worst-case execution time analysis; Aerospace electronics; Automotive engineering; Clocks; Delay; Hardware; Real time systems; Software safety; Synchronization; Synchronous generators; Timing; Esterel; Synchronous programming; Worst-case Execution Time (WCET) analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
978-1-6055-8497-3
Type
conf
Filename
5227113
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