Exploiting “Architecture for Verification” to streamline the verification process

A typical hardware development flow starts the verification process concurrently with RTL, but the overall schedule becomes limited by the effort required to complete all the necessary verification tasks. Being the limiting factor, verification schedules become unpredictable, often resulting in slippage of the tapeout dates. This paper looks at ways to restructure the flow to complete a significant part of this effort during the architectural phase of the project, prior to the start of RTL. This front-loading of the schedule allows a smaller verification team to complete the process with a tighter schedule.