DocumentCode
500911
Title
Verification problems in reusing internal design components
Author
Stapleton, Warren ; Tobin, Paul
Author_Institution
AMD, Austin, TX, USA
fYear
2009
fDate
26-31 July 2009
Firstpage
209
Lastpage
211
Abstract
Large SOCs provide new verification challenges. This paper discusses how the SOC/IP paradigm has impacted AMD, and highlights some of the design issues that you need to consider if you are going to embark on implementing the SOC/IP approach on large projects in your own company.
Keywords
formal verification; logic design; system-on-chip; AMD; SOC/IP paradigm; component reuse; internal design component; verification problem; Bridges; Design optimization; Energy management; Formal verification; Microprogramming; Power system management; Process design; Production; Qualifications; Software design; IP; SOC; Validation; Verification;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
978-1-6055-8497-3
Type
conf
Filename
5227169
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