Self-biased 0.13- µm CMOS 2.4-GHz Class E cascode power amplifier

Efficiency enhancement techniques in switched Class E power amplifier is usually obtained at the expense of the supply voltage. In cascode topology the supply voltage is limited by the breakdown voltage of the common-gate transistor. So a self biased technique is used at the common-gate to allow RF swing at the gate to boost the biasing voltage above VDD. This enables us to design the PA such that the cascode transistor has the same maximum drain-gate voltage. Consequently, we can have a larger signal swing at the output before encountering the breakdown. By using this combination, the gate of the NMOS is boosted above VDD and the power consumption is reduced. Simulation results using 0.13-mum CMOS technology demonstrate 25.8 dBm output power with 38.8% drain efficiency at 2.4 GHz.