A novel low-power and high-speed dynamic CMOS logic circuit technique

Domino CMOS logic finds a wide variety of applications due to their high speed and low device count. In conventional CMOS domino logic, either the dynamic-node capacitor, C_L is precharged to V_DD during the precharge phase or predischarged to 0 V. The first precharging scheme is more suitable when logic "0" occurrence is more probable at the output due to the large saving in power consumption. On the other hand, the second predischarging scheme is more suitable when logic "1" is more probable at the output. In this paper, we will propose a novel technique to speed up the operation and minimize power consumption when there is an equal probability of occurrence of logic "0" and logic "1". This technique depends on precharging the dynamic node to V_DD/2 instead of V_DD during the precharge phase. Then, during the evaluation phase, the dynamic-node voltage will be either increased to V_DD or decreased to 0 V depending on the state of the inputs. This, of course, saves much of the time and power consumption because discharging the dynamic node from V_DD/2 to 0 V is much faster and consumes less power consumption than discharging it from V_DD to 0 V. Also, the discharging process and noise margin will be enhanced by virtue of the fact that the time interval during which the keeper combats the discharging process is relatively very small. The proposed technique will be simulated for the 0.13 mum technology with V_DD=1.2 V. Simulation results show that about 75% was shaved from the cycle time for the case of "0" and "1" outputs at the expense of an additional silicon area.