Implementation of high VT turn-on in low-voltage SCR devices

A novel design approach for low-voltage ESD protection clamps is suggested based on the use of free pseudo high threshold voltage SCR structures. The method is experimentally validated for a 0.18 mum 1.8 V/5 V dual gate oxide CMOS process where free high threshold voltage (V_T) LVTSCR and Drain extended NMOS-SCR structures were formed by combining the thick 120 A gate oxide used for 5 V devices with additional low voltage PWELL through poly implants used for the 1.8 V devices. The physical mechanism of the forming of pseudo high V_T characteristics is explained by means of numerical simulation. Low-voltage pulsed turn-on and turn-off characteristics have been demonstrated under low DC leakage of the devices.