Title :
Development of a high throughput LDPC codec with 1Gb/s and OFDM transmission system utilizing MBD
Author :
Maehata, Takashi
Author_Institution :
Sumitomo Electr. Ind., Japan
Abstract :
Low-density parity-check (LDPC) codes, which are among the most powerful error correcting codes, can achieve performance close to the Shannon limit. It is difficult to evaluate the performance of LDPC codes by software simulation only, because it takes much time and labor. To solve this problem, we have developed the design environment for designing and evaluating LDPC codes on hardware.
Keywords :
OFDM modulation; error correction codes; parity check codes; MBD; OFDM transmission system; Shannon limit; error correcting codes; high throughput LDPC codec; low-density parity-check codes; Algorithm design and analysis; Codecs; Error correction codes; Field programmable gate arrays; HDTV; Hardware design languages; Magnetic recording; OFDM; Parity check codes; Throughput; Codec; FPGA; HDL Code Generation; HILS; LDPC; MBD; Model-Based Development;
Conference_Titel :
ICCAS-SICE, 2009
Conference_Location :
Fukuoka
Print_ISBN :
978-4-907764-34-0
Electronic_ISBN :
978-4-907764-33-3
