High mechanical stress applied to FD-SOI transistors using ultra-thin silicon membranes

The study of electron mobility enhancement in FD-SOI transistors induced by high mechanical stress is nowadays of particular interest. In this contribution we investigate an original method to apply high values of biaxial stress: the integration of submicronic FD-SOI transistors on ultra-thin silicon membranes. The membranes are micromachined on SOI substrates that facilitates the control of the membrane thickness down to a few hundred nanometers. High values of biaxial stress can thus be applied on the transistor channel without the drawbacks of conventional methods. We present a study of piezoresistance effect in FD-SOI transistors using a 750 nm thick membrane. The piezoresistive longitudinal coefficient obtained for strained-SOI wafer (240*10^-12 Pa^-1) is in good agreement with the results obtained by the four-probe method. Stress values as high as 0.5 GPa have been obtained using 1 bar applied pressure.