Characterization, modelling and simulation of Sub-45nm SOI devices

The silicon CMOS technology is evolving following aggressive scaling rules which lead to severe physical limits. Different solutions have been proposed during the last years to bypass these limitations. Among others, ultrathin-body and BOX (UTB²) Silicon-On-Insulator technology has been shown to provide excellent scalability properties beyond the 22 nm node. The existing models for characterization, modelling and simulation of ultrathin SOI devices must be revisited from the wafer level to the transistor level. In this paper we review our recent results on SOI wafer characterization, SOI transistors characterization and SOI-transistors simulation. All these results update and highlight the possibilities of SOI technology.