Title :
Characterization, modelling and simulation of Sub-45nm SOI devices
Author :
Rodriguez, Noel ; Gámiz, Francisco ; Cristoloveanu, Sorin
Author_Institution :
Fac. de Ciencias, Dept. de Electron. y Tecnol. de Comput., Univ. de Granada, Granada, Spain
Abstract :
The silicon CMOS technology is evolving following aggressive scaling rules which lead to severe physical limits. Different solutions have been proposed during the last years to bypass these limitations. Among others, ultrathin-body and BOX (UTB2) Silicon-On-Insulator technology has been shown to provide excellent scalability properties beyond the 22 nm node. The existing models for characterization, modelling and simulation of ultrathin SOI devices must be revisited from the wafer level to the transistor level. In this paper we review our recent results on SOI wafer characterization, SOI transistors characterization and SOI-transistors simulation. All these results update and highlight the possibilities of SOI technology.
Keywords :
CMOS integrated circuits; integrated circuit modelling; silicon-on-insulator; CMOS technology; scaling rules; silicon-on-insulator; size 22 nm; size 45 nm; transistor level modelling; wafer level modelling; CMOS technology; Insulation; Interface states; Isolation technology; MOSFETs; Semiconductor device modeling; Semiconductor films; Silicon on insulator technology; Threshold voltage; Transistors;
Conference_Titel :
Semiconductor Conference, 2009. CAS 2009. International
Conference_Location :
Sinaia
Print_ISBN :
978-1-4244-4413-7
DOI :
10.1109/SMICND.2009.5336609