Electro-thermal modeling of nano-scale devices

Author

Vasileska, D. ; Raleva, K. ; Goodnick, S.M.

Author_Institution

Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA

fYear

2009

fDate

7-9 Oct. 2009

Firstpage

195

Lastpage

196

Abstract

In this paper we present simulation results obtained with our electro-thermal device simulator when modeling different technology generations of FD-SOI devices. In particular, we stress out the importance of the temperature boundary conditions for digital and analog circuits and the use of the full model which takes into account both temperature and thickness dependence (which is particularly important for thin silicon films) of the thermal conductivity.

Keywords

analogue circuits; circuit simulation; digital circuits; elemental semiconductors; nanoelectronics; silicon; silicon-on-insulator; thermal conductivity; Si; analog circuits; digital circuits; electro-thermal device simulator; electro-thermal modeling; fully-depleted silicon-on-insulator device; nanoscale devices; temperature boundary conditions; thermal conductivity; thin silicon films; Analog circuits; Boundary conditions; Circuit simulation; Conductive films; Nanoscale devices; Semiconductor films; Silicon; Temperature dependence; Thermal conductivity; Thermal stresses; FDSOI devices; electro-thermal modeling; particle-based device simulations;

fLanguage

English

Publisher

ieee

Conference_Titel

Thermal Investigations of ICs and Systems, 2009. THERMINIC 2009. 15th International Workshop on

Conference_Location

Leuven

Print_ISBN

978-1-4244-5881-3

Type

conf

Filename

5340062