Title :
A new power analysis resistant SRAM cell
Author :
Arikan, Ebru ; Ataman, Atilla
Author_Institution :
TUBITAK - UEKAE, Gebze, Turkey
Abstract :
The power consumption of a standard SRAM during read/write operations is dependent on the address applied, the data accessed, and the type of access (read/write). The power analysis resistant SRAM structure developed during the Project ¿SCARD¿ (Side Channel Analysis Resistant Design Flow) of the European Community 6. Framework Program reduces the dependency of power consumption on data and address compared to standard SRAM at the expense of higher power and silicon area consumption. In this work a new SRAM primitive cell structure is proposed to reduce the power consumption and its dependency to data to be written.
Keywords :
SRAM chips; power electronics; SCARD; SRAM primitive cell structure; framework program; power analysis resistant SRAM cell; power analysis resistant SRAM structure; power consumption; read/write operations; side channel analysis resistant design flow; silicon area consumption; standard SRAM; static random access memory; Capacitance; Charge transfer; Cryptography; Data security; Energy consumption; Hardware; Logic devices; Random access memory; Read-write memory; Silicon;
Conference_Titel :
Electrical and Electronics Engineering, 2009. ELECO 2009. International Conference on
Conference_Location :
Bursa
Print_ISBN :
978-1-4244-5106-7
Electronic_ISBN :
978-9944-89-818-8